Physical Design Engineer; PnR​/PPA​/Timing Closure

Physical Design Engineer (PnR / PPA / Timing Closure)

Wipro Limited is a leading technology services and consulting company focused on building innovative solutions that address clients' most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world.

We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes.

• Drive block-level physical design implementation from netlist to GDSII.
• Perform floor planning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Optimize designs for Power, Performance, and Area (PPA) targets.
• Achieve timing closure across multiple corners and modes.
• Analyze and resolve setup, hold, transition, capacitance, and noise violations.
• Develop and maintain timing constraints (SDC) and STA signoff methodologies.
• Perform EMIR (Electromigration & IR Drop) analysis and closure.
• Collaborate with RTL, DFT, STA, and Signoff teams to ensure successful tapeout.
• Debug physical design issues and drive design convergence within project schedules.

• Strong experience in Physical Design and PnR flow.
• Hands-on expertise in:
• Floor planning
• Placement & Optimization
• Clock Tree Synthesis (CTS)
• Routing
• Timing Closure
• Static Timing Analysis (STA)
• Timing Constraints (SDC)
• EMIR Analysis
• PPA Optimization
• Experience with industry-standard EDA tools such as:
• Synopsys Fusion Compiler / ICC2
• Prime Time
• Cadence Innovus (optional)
• Red Hawk / Voltus (EMIR)
• Good understanding of low-power design techniques and signoff methodologies.

• Bachelor's or Master's degree in Electrical/Electronics Engineering.
• Experience in advanced nodes (7nm/5nm/3nm preferred).
• Strong debugging and problem-solving skills.
• Experience working with cross-functional silicon teams.

VLSI Physical Place and Route.

Experience:

3-5 Years.

The expected compensation for this role ranges from $45,000 to $121,000. Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.

Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law. Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.

Applications from veterans and people with disabilities are explicitly welcome.