DFT Engineer; Scan​/MBIST​/ATPG

Position: DFT Engineer (Scan / MBIST / ATPG)

Location: Mountain View CA (On-site)

Hire Type: Full Time / Contract

We are seeking a DFT Engineer with hands‑on experience in Scan, MBIST, ATPG generation, and pattern simulation for complex SoC/IP designs.

• Develop and implement Design‑for‑Test (DFT) architecture for IPs and SoCs.
• Perform Scan insertion and Scan chain verification.
• Integrate and validate MBIST solutions for embedded memories.
• Generate ATPG patterns for stuck‑at, transition, and other manufacturing fault models.
• Execute ATPG simulation and pattern verification to ensure coverage and pattern quality.
• Analyze and improve fault coverage while reducing pattern count.
• Debug DFT‑related issues during implementation and verification.
• Collaborate with RTL, Physical Design, Verification, and Test Engineering teams.
• Support silicon bring‑up and production test activities when required.

• Strong understanding of DFT fundamentals.
• Scan Architecture
• Scan Insertion
• Scan Compression
• MBIST Integration
• ATPG Pattern Generation
• ATPG Simulation
• Fault Coverage Analysis
• Experience with industry‑standard DFT tools such as:
• Synopsys DFT Compiler
• TetraMAX / TestMAX ATPG
• Good knowledge of Verilog/System Verilog and simulation environments.
• Familiarity with manufacturing test concepts and silicon debug.

• Experience with large SoC or CPU/GPU designs.
• Knowledge of IJTAG, Boundary Scan (JTAG), LBIST, and Test Compression.
• Experience supporting post‑silicon test and yield improvement activities