Silicon Physical Verification Engineer, Google Cloud

Silicon Physical Verification Engineer, Google Cloud Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in ASIC physical design flows with emphasis on physical verification convergence and tapeout signoff.
• Experience in physical verification tools, Python, Tcl, or Perl scripting.

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in place and route (PnR) tools like fusion compiler or innovus with physical convergence.
• Experience in padrings, bumps, redistribution layer (RDL), and IP integration (e.g., memories, input/outputs, and analog IPs).
• Knowledge of semiconductor device physics and translator characteristics.

• Own and perform physical verification steps including design rule check (DRC), layout versus schematic (LVS), electrical rule check (ERC), design for manufacturing (DFM) at the block, subsystem, and full chip level.
• Own and define process flow and methodology for full chip assembly and tapeout signoff.
• Work with floorplan and physical design engineers to drive physical verification convergence.
• Perform technical physical evaluations of vendors, process nodes, and intellectual property (IP).
• Contribute to design methodologies and automation scripts for physical verification steps.

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