Physical Design Engineer

We are seeking a skilled Physical Design Engineer with strong expertise in Place & Route (PnR), PPA optimization, and timing closure for advanced semiconductor designs. The ideal candidate will drive block-level physical implementation from netlist to GDSII while ensuring performance, power, and area targets are met.

Key Responsibilities:

• Execute end-to-end physical design flow including floor planning, placement, CTS, routing, and signoff.
• Optimize designs for Power, Performance, and Area (PPA).
• Perform STA, timing closure, and resolve setup/hold, transition, capacitance, and noise violations.
• Develop and manage timing constraints (SDC) and signoff methodologies.
• Conduct EMIR analysis and support physical verification.
• Collaborate with RTL, DFT, STA, and signoff teams for successful tapeout.

Required Skills:

• Strong hands-on experience with Physical Design and PnR flow.
• Expertise in floor planning, placement optimization, CTS, routing, STA, timing closure, SDC, and PPA optimization.
• Experience with EDA tools such as Synopsys Fusion Compiler/ICC2, Prime Time, Cadence Innovus, Red Hawk, or Voltus
  .
• Understanding of low-power design techniques and semiconductor signoff processes.
• Experience with advanced technology nodes (7nm/5nm/3nm preferred).

Qualifications:

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field.
• Strong debugging skills and experience working with cross-functional silicon teams.