Senior RTL Design Engineer

Job Overview

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct‑to‑consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 10 years of experience with IP Development or Integration.
• Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language).
• Experience with a scripting language (e.g., Python or Perl).

• Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with ASIC design methodologies for clock domain checks, reset checks, and low‑power design.
• Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
• Knowledge of high‑performance and low‑power design techniques.
• Knowledge of ASIC Verification, DFT, synthesis, STA, or physical design.
• Knowledge of FPGA and emulation platforms.

• Define the detailed microarchitecture specifications for silicon subsystems and small to medium‑sized intellectual property blocks to meet performance, area, and power requirements.
• Integrate internal and external intellectual property (IP) blocks seamlessly into complex silicon designs and multi‑component subsystems.
• Execute production‑grade RTL coding, debug intricate function and performance simulation issues, and conduct standard lint, clock domain crossing, formal verification, and unified power format checks.
• Partner closely with validation teams during test plan formulation and coverage analysis for comprehensive subsystem and chip‑level design verification.
• Drive technical alignment across multi‑disciplinary and multi‑site engineering groups to resolve architectural issues and ensure successful product delivery.

US: $192,000 - $279,000 (USD) + 20% bonus target + equity + benefits.

Google is a proud equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity or expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law.

English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies:
Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc.

stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.