More jobs:
Senior ASIC DFT Engineer: Lead Subsystem DFT & Debug
Job in
Mountain View, Santa Clara County, California, 94039, USA
Listed on 2026-07-20
Listing for:
Google
Full Time
position Listed on 2026-07-20
Job specializations:
-
Engineering
Hardware Engineer, Test Engineer, Electronics Engineer
Job Description & How to Apply Below
Google is seeking a Senior ASIC DFT Engineer, Silicon, to lead DFT architecture across SoCs, collaborating with RTL, Physical Design, and Product teams.
The role requires 8+ years in DFT, experience with Tessent, Genus, Fusion Compiler, Simvision, and scripting in Python or Perl to automate flows. You will drive scan implementation, MBIST, ATPG, and IJTAG tooling.
This is a hands-on role with end-to-end DFT from architecture to silicon debug within Google's innovative hardware team.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
To View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
Search for further Jobs Here:
×