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Senior RTL Design Engineer — Lead - ASICs; Equity

Job in Mountain View, Santa Clara County, California, 94039, USA
Listing for: Google
Full Time position
Listed on 2026-07-23
Job specializations:
  • Engineering
    Hardware Engineer, Test Engineer, Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 200175 - 270825 USD Yearly USD 200175.00 270825.00 YEAR
Job Description & How to Apply Below
Position: Senior RTL Design Engineer — Lead High-Performance ASICs (Equity)

Google is seeking a senior hardware engineer in Mountain View to define microarchitectures for silicon subsystems and integrate IP blocks into complex designs. You will perform RTL coding, simulations, and formal verification while coordinating with validation teams to ensure robust chip delivery.

The role emphasizes cross‑team collaboration across sites, architecture decisions, and ownership of critical aspects of silicon design for high performance and efficiency.

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Position Requirements
10+ Years work experience
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