Senior FPGA Modem Engineer

Senior FPGA Modem Engineer

Logos Space is a Low Earth Orbit (LEO) satellite system purpose-built to serve the connectivity needs of the commercial enterprise users and government users. We will help fill an important gap in the market, providing resilient, high-performance satellite-based connectivity services to enterprise and government customers worldwide. Business customers have contracts with agreed-upon performance standards for their broadband, and Logos will build these capabilities into the system from the beginning.

Speed and reliability are the foundation of the system. Logos is designed to extend cloud and data center network connectivity anywhere in the world to fixed, seaborne, and airborne terminals.

The Baseband Modem hardware team at Logos Space is building a high-performance digital modem payload for the Logos LEO satellite system that supports high-throughput, secure, reliable and resilient communications with an emphasis on waveform flexibility using Software Defined Radio (SDR) technology.

As a Senior FPGA Modem Engineer, you will design, implement, verify and release FPGA-based modem solutions for end-to-end wireless satellite communications links. You will work closely with the modem systems team on realization of waveform designs using fixed-point FPGA digital hardware and DSP blocks. This role is an exciting opportunity to help build a LEO satellite communications system from the ground up using cutting-edge FPGA technology.

We are looking for digital FPGA hardware engineers who can work well in a fast-paced environment, turn sometimes ambiguous requirements into practical hardware implementations, and collaborate closely with adjacent teams.

• Own one or more FPGA-based modem chains through all development phases, from micro-architecture through to lab deployment.
• Define the micro-architecture of high-rate FPGA modem blocks and surrounding digital infrastructure. Implement designs using System Verilog or Verilog.
• Develop block-level and end-to-end self-checking hardware verification environments using golden reference models provided by the modem systems team.
• Develop FPGA synthesis and place and route build scripts including timing and placement constraints. Analyze results and implement design changes required to close timing and meet system-level FPGA power and resource requirements.
• Define and implement clean hardware/software interfaces, including registers, configuration, telemetry, fault and status signaling, and test hooks.
• Conduct code and design reviews and participate in multi-functional reviews.
• Collaborate with systems architects, HW engineering design teams and FW/SW design teams for lab bring-up of boards combining FPGA, firmware, RF, and Networking functions.
• Mentor junior engineers and provide technical leadership on FPGA best practices.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field.
• A minimum of 10+ years experience in design, development and implementation of wireless baseband modems using FPGA devices. Equivalent experience in ASIC modem design will also receive consideration.
• Proficiency in one or more HDL programming languages such as VHDL, Verilog, or System Verilog.
• Experience writing verification frameworks using System Verilog/UVM, Cocotb or transactional-level modeling.
• Thorough knowledge of modern FPGA architecture including experience with advanced floor planning clock-domain crossing (CDC) analysis, false-path isolation, and timing closure techniques . Experience using these techniques with AMD Ultra Scale+ and Versal FPGA families is highly preferred.
• Deep understanding of Digital Front End (DFE) architectures, including digital up/down conversion (DUC/DDC), interpolation/decimation filters, and interfacing with high-speed ADCs and DACs.
• Experience with industry-standard bus interfaces such as AXI and AXI-streaming and high-speed interfaces such as DDR4/5, 10/40/100 Gb Ethernet and SERDES interfaces like JESD-204B/C, Aurora and Interlaken.
• Experience with FPGA tool chains and workflows such as AMD Vivado, including simulation, synthesis, place-and-route,…