Senior Director, IP and Custom Circuits Development

** Overview*
* Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, One Drive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions.

Our focus is on smart growth, high efficiency, and delivering trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

As Microsoft's cloud business continues to grow, the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the AI SoC Development team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware.

We are looking for an engineer with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a  
** Senior Director, IP and Custom Circuits Development
** to join the team.

** Responsibilities*
* + Lead and manage Custom IPs like High speed D2D, SRAMs, Register Files and other differentiating IP development team

+ Ensure high quality and on-time delivery of custom IPs to Soc teams internal to Microsoft

+ Initiatives to strengthen the team and attract talents

+ Identify opportunities to develop new differentiating IPs for the SoC teams

+ Strategize on build vs buy on IPs

+ Close interaction with senior experts of SoC design and architecture teams on IP definitions

** Qualifications*
* ** Required/minimum qualifications*
* + Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 7+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 10+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience. OR Equivalent Experience.

** Other Requirements:*
* + Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check:
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

+ This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US.

residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

*
* Preferred Qualifications:

*
* + 17+ years of experience in leading High-Speed Serial and/or Parallel IO architecture and design with BSEE or 15+ years of experience in the same with MSEE in Electrical Engineering

+ Experience in leading large cross-site organizations

+ Familiarity with SRAM and/or Register File designs

+

Experience with test Chip developments with…