Senior CPU RTL Design Engineer

Senior CPU RTL Design Engineer

Driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in implementation of CPU cache subsystems, including load-store unit or private/shared L2/L3 designs. Experience with RTL language (e.g. System Verilog) and related design processes (e.g., Lint, UPF).

Preferred qualifications:

PhD in Electrical Engineering or Computer Science, or a related field. Experience leading front-end design for modern processor components or AI accelerators. Experience with ARM Instruction Set Architecture or CPU subsystems. Experience with SoC design, architecture, and integration.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits.

Responsibilities:

• Engage in developing CPU cache subsystems, focusing on RTL design and microarchitecture for future CPU generations.
• Collaborate with performance, architecture, and software teams to evaluate trade-offs and suggest microarchitectural improvements that boost performance.
• Deliver high-quality designs on time while articulating the advantages and disadvantages of various microarchitecture updates.
• Partner with verification, power, and physical design teams to ensure designs meet area, power, and frequency targets.
• Optimize cache unit design and coordinate with other design units within CPU subsystems to achieve excellent power, performance, and area.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law.