Silicon Validation Engineer

What MatX Is Building

MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity and other key technologies.

Here Own silicon bring-up and validation activities from first power-on through feature validation, characterization, qualification, and production readiness.

Develop and execute validation plans for chip-level and SiP-level functionality, performance, reliability, and system behavior.

Validate power-up, initialization, boot, reset, recovery, power-management, and error-handling flows.

Validate compute, memory, interconnect, data-movement, high-speed interface, and package-level functionality.

Create and execute high-stress workloads that exercise bandwidth, latency, concurrency, coherency, error handling, and long-duration operation.

Work across Top-level DV, Palladium emulation, lab validation, and package validation to shift validation left and improve correlation between environments.

Reuse and adapt validation scenarios across simulation, emulation, and silicon where practical.

Bring up complex hardware and debug failures using registers, logs, traces, waveforms, firmware output, diagnostics, protocol analyzers, and lab equipment.

Analyze failures across RTL, firmware, drivers, software, board, package, and silicon boundaries.

Work closely with firmware teams to debug low-level software and firmware interactions with the hardware.

Review firmware, embedded software, drivers, and diagnostic code as part of failure analysis, without being responsible for their primary development.

Collaborate with architecture and design teams to understand intended behavior, microarchitecture, performance expectations, and available debug mechanisms.

Collaborate with DV and emulation engineers to reproduce silicon issues in pre-silicon environments and identify issues before silicon arrives.

Define validation, observability, and debug requirements needed for effective silicon and SiP-level troubleshooting.

Support package-level validation, including connectivity, power, reset, signal integrity, thermal behavior, and die-to-die interactions.

Drive root-cause investigations and coordinate cross-functional debug until issues are understood, contained, and resolved.

Develop scripts, test infrastructure, automation, and data-analysis capabilities that improve validation execution and failure triage.

Track validation coverage, execution status, failures, risks, and readiness against product milestones.

Improve SiP V&V methodology, automation, debug capability, and overall engineering productivity.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• Strong hands-on experience in silicon validation, post-silicon bring-up, hardware emulation, Top-level DV, or a closely related field.
• Experience validating complex SoCs, accelerators, compute devices, or highly integrated silicon products.
• Strong understanding of digital hardware, SoC architecture, and hardware-firmware interactions.
• Proven ability to debug complex failures across hardware, firmware, software, package, and validation-environment boundaries.
• Experience working in a laboratory environment with real silicon and hardware platforms.
• Experience using…