R&D Engineer
Listed on 2026-08-31
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Engineering
Hardware Engineer, Test Engineer, Electronics Engineer
R&D Engineer
Location:
Mountain View, CA Pay Rate:
Starting at $107.36 per hour
Schedule:
Monday–Friday, 40 hours per week
We are seeking an experienced R&D Engineer specializing in FPGA design, prototyping, and hardware-assisted verification. This position will map complex ASIC and SoC designs onto high-capacity FPGA platforms to accelerate pre-silicon validation, system verification, and embedded software development. The ideal candidate will have strong RTL design, FPGA architecture, timing analysis, debugging, and scripting experience.
Key Responsibilities- Convert large, complex ASIC and SoC designs into single- or multi-FPGA prototype systems.
- Develop and implement FPGA designs using Verilog, System Verilog, or VHDL.
- Design high-speed protocol logic, interfaces, and speed adapters.
- Work with industry-standard interfaces and protocols, including PCIe, AXI, UCIe, USB, and DDR.
- Perform FPGA synthesis, partitioning, placement, routing, and timing closure.
- Analyze and resolve complex timing constraints, RTL issues, and hardware defects.
- Debug FPGA prototypes using advanced hardware and software debugging tools.
- Develop Python and Tcl scripts to automate build flows, testing, and design processes.
- Support system integration, hardware bring-up, verification, and validation.
- Collaborate with internal engineering teams and customers to support FPGA platform deployment.
- Document designs, technical findings, test results, and troubleshooting procedures.
- Strong FPGA design, prototyping, emulation, or hardware verification experience.
- Proficiency in Verilog, System Verilog, or VHDL.
- Experience with FPGA architectures from AMD/Xilinx or Intel/Altera.
- Strong understanding of RTL design, synthesis, timing analysis, and timing closure.
- Proficiency in Python and Tcl scripting.
- Experience debugging complex FPGA, ASIC, or SoC designs.
- Familiarity with high-speed interfaces and protocols such as PCIe, USB, DDR, AXI, or UCIe.
- Strong analytical, troubleshooting, and problem-solving abilities.
- Effective written and verbal communication skills.
- Ability to work independently and collaborate with cross-functional engineering teams.
Benefits (employee contribution):
- Health insurance
- Health savings account
- Dental insurance
- Vision insurance
- Flexible spending accounts
- Life insurance
- Retirement plan
All qualified applicants will receive consideration for employment without regard to age, race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Rate of pay within the stated range will depend on the qualification of the applicant. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. Pursuant to applicable state and municipal Fair Chance Laws and Ordinances, we will consider for employment-qualified applicants with arrest and conviction records.
For Los Angeles, CA applicants:
Qualified applications with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act.
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