PCB Layout Engineer - AI Compute Hardware

What MatX Is Building

MatX is building next-generation AI compute infrastructure for large-scale LLM training and inference. We are looking for an experienced PCB Layout Engineer to design and deliver high-speed, high-power, high-density printed circuit boards for our AI chip, compute tray, and rack-scale platform. This is a hands-on role where layout quality directly impacts signal integrity, power integrity, and system performance.

• Own PCB layout from floor planning through final Gerber release for complex, high-layer-count boards (AI accelerator boards, compute trays, backplanes)

• Design high-speed differential pair and controlled impedance routing for PCIe Gen5/6, CXL, and Ethernet 112G/224G interfaces, including length matching and timing constraints per SI/PI guidelines

• Plan stack-ups (layer assignment, impedance control, via structure, laminate selection) and place/route complex BGA packages, including AI ASICs

• Design power delivery networks (PDN) — VRM placement, decoupling capacitors, and power planes to meet PI requirements, partnering with SI/PI engineers on simulation and pre/post-layout analysis

• Ensure DFM/DFT/DFA compliance (test points, via-in-pad, back-drill, assembly constraints) and coordinate with mechanical engineers on board outline, keep-outs, and chassis constraints

• Lead design, layout, and DFM reviews with JDM/ODM partners, and manage release packages (Gerbers, fabrication notes, stackup docs, footprint libraries)

• Support bring-up, debug, and signal probing to resolve layout-related issues

• 7+ years of PCB layout experience, including complex multi-layer boards (20+ layers) for server, AI compute, networking, or similar high-performance hardware

• Strong proficiency in Cadence Allegro (or equivalent EDA tool), with deep expertise in high-speed design: differential pair routing, impedance control, length matching, reference planes, and via optimization

• Experience with fine-pitch BGA placement/routing for AI ASICs, GPUs, or high-density packages, and hands-on work with high-speed interfaces (PCIe Gen5/6, CXL, DDR5, 112G/224G Ser Des)

• Strong understanding of PDN design (VRM placement, decoupling strategy, power planes, current return paths) and stack-up design (layer count, impedance control, material selection, e.g. Megtron 6/8/9, TU-953Q)

• Familiarity with back-drilling, via-in-pad, and other advanced fabrication techniques, plus DFM/DFT requirements (test point coverage, copper balance, solder mask, assembly constraints)

• Ability to interpret SI/PI simulation results and incorporate feedback into layout

• Experience releasing fabrication packages (Gerbers, drill files, stackup specs) and working directly with PCB fabricators and JDM/ODM partners on high-speed, high-layer-count boards

• Experience with 5nm or 3nm and below AI ASIC board layout, ultra-fine pitch BGA, high-density routing

• Experience with 224G PAM4 high-speed interface routing and material selection

• Knowledge of fiber weave effect mitigation — routing at 45°, spread glass laminates

• Familiarity with OCP Open Rack board form factors and mechanical constraints

• Experience with power integrity simulation tools (Ansys SIwave, Cadence Sigrity)

• Background in EMI/EMC design, stitching vias, ground guard traces, and shielding techniques

The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job-related skills, and relevant education and training. Career length is only a guideline for compensation.

• Early Career - $160,000 - $275,000 + equity

• Mid Career - $175,000 - $400,000 + equity

• Senior Career - $250,000 - $600,000 + equity

What We Offer

• Time off: 4 weeks PTO (accrued) + 12 company Holidays + up to 3 weeks remote…