RTL Design Engineer, Silicon; ASIC/IP
Job in
Mountain View, Santa Clara County, California, 94039, USA
Listed on 2026-09-02
Listing for:
Google Inc.
Full Time
position Listed on 2026-09-02
Job specializations:
-
Engineering
Hardware Engineer, Electronics Engineer, Test Engineer, Systems Engineer
Job Description & How to Apply Below
Google Mountain View, CA, is seeking an RTL Design Engineer in Silicon to contribute to custom silicon powering Google devices. You will define microarchitecture, integrate IP, and perform RTL coding and verification.
Requirements include a Bachelor's in EE/CE/CS or related field, 4 years of IP development or integration experience, and proficiency in Verilog or VHDL; scripting in Python or Perl is preferred. Master/PhD plus ASIC/DFT experience preferred.
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