Silicon RTL Design Engineer Impact IP & ASIC
Job in
Mountain View, Santa Clara County, California, 94039, USA
Listed on 2026-09-09
Listing for:
Google
Full Time
position Listed on 2026-09-09
Job specializations:
-
Engineering
Hardware Engineer, Electronics Engineer, Systems Engineer, Test Engineer
Job Description & How to Apply Below
Google in Mountain View, CA is seeking a Mid-level RTL Design Engineer to drive micro-architecture definition and IP integration for an ASIC/subsystem. You will code in RTL languages, perform complex simulations, and contribute to synthesis, timing, and power closure for silicon bring-up.
The role requires 5+ years in RTL design, IP integration, and scripting with Perl or Python, with a bias toward low-power and high-performance designs. Eligible for base salary with bonus and equity.
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