Senior CPU Architecture and Performance Architect

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 10 years of experience in microprocessor architecture, microarchitecture, performance and design.
• Experience with CPU architecture with CPU blocks, along with performance modeling, analysis, correlation, and workload characterization.
• Experience with processor instruction set architecture (e.g., ARM, RISC-V, x86) and system software components, such as Linux, drivers, and runtime.

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in performance modeling, debugging, and demonstrating the benefits of new ideas.
• Knowledge of processor instruction set architecture (e.g., ARM, RISC-V, x86).
• Ability to generate innovative microarchitectural ideas to improve performance in actual silicon.
• Strong critical thinking, communication, and advocacy skills.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

Learn more about benefits at Google.

• Deliver solutions to complex problems that may be ambiguous and/or lacking clear precedent. These problems include CPU performance, microarchitecture design, tool infrastructure, methodology, and so on.
• Plan, drive, and evaluate ARM’s architecture features from both architecture and performance angles.
• Define and write CPU subsystem architecture specifications.
• Lead the collaboration with RTL, design verification, and physical design teams to develop a high performance and efficient CPU implementation.
• Drive performance correlation between the performance model and RTL implementation and perform pre-silicon and post-silicon performance bug triage.