Design Verification Engineer – Compute

• Contribute to MatX’s verification methodology with a scalable solution across blocks, subsystems, full-chip, and system-level validation
• Own portions of verification execution at subsystem and chip level
• Create test benches, tests, and related artifacts to achieve structural and functional coverage closure
• Plan and drive intermediate and sign-off reviews on verification test plans and execution progress
• Drive verification closure toward silicon milestones, including design freeze and tapeout
• Help make AI models run as efficiently as allowed by physics through hardware verification work

• At least 5 years of silicon design-verification experience
• End-to-end, concept-to-silicon tapeout experience, driving verification from architecture and/or design specification through design freeze, tapeout, and production silicon
• Production experience with System Verilog and UVM
• Experience with assertion-based verification (ABV)
• Comfort with formal and simulated verification
• Experience with Python, C/C++, and similar scripting and programming languages for verification and silicon modeling
• Production experience creating portable tests and drivers for silicon validation and post-silicon debug
• Strong understanding of silicon micro-architecture and design concepts used in high-performance compute, including CPUs, GPUs, and accelerators
• Understanding of memory management and related functionalities
• Must be authorized to work in the United States
• Must be able to work from the Mountain View offices Tuesday-Thursday
• Must comply with applicable U.S. export control laws without obtaining an export-control license

Demonstrates extensive experience in silicon design verification, including end-to-end tapeout processes and the creation of test benches and tests for functional coverage. Proficient in using System Verilog, UVM, and programming languages like Python and C/C++ for verification and silicon modeling.

• Silicon Design Verification
• System Verilog
• UVM
• Assertion-Based Verification (ABV)
• End-to-End Tapeout Experience

• Silicon Design Verification
• System Verilog
• UVM
• Assertion-Based Verification (ABV)
• Python
• C/C++
• Testbench Creation
• Functional Coverage Closure
• Silicon Micro-Architecture
• Memory Management

• High-Performance Compute
• Design Freeze
• Tapeout
• Silicon Validation
• Post-Silicon Debug