ASIC Design Engineer IV

Overview

• The successful candidate is considered an emerging authority, who applies extensive technical expertise, develops technical solutions to complex problems and exercises considerable latitude in determining objectives and approaches to assignment.
• As such, you will be part of a team of ASIC design engineers to create a design document that defines the chip's features, performance, and internal components.
• You will finish developing, enhancing, and debugging the VHDL/Verifog for the chip.
• This includes verifying the functionality of the design on an HDL simulator (such as Model Sim or Xcelium) and synthesis with Synopsys or Genus.
• You will perform clock domain crossing (CDC) & reset domain crossing (RDC) verification, Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design.
• You will develop and port the RTL to an FPGA prototyping board.
• You will perform place and route of the netlist prior to tapeout, this includes clock tree synthesis (CTS).
• You will also run static timing analysis and power analysis after the CTS and place and route.
• Packaging and an evaluation board for the physical chip must also be performed.
• As an ASIC Design Engineer, you will develop and maintain technical procedures, documentation, and manuals and compile and analyze operational data and conduct tests to establish standards for new designs or modifications to existing equipment, systems, or processes.

• The successful candidate is considered an emerging authority, who applies extensive technical expertise, develops technical solutions to complex problems and exercises considerable latitude in determining objectives and approaches to assignment.
• As such, you will be part of a team of ASIC design engineers to create a design document that defines the chip's features, performance, and internal components.
• You will finish developing, enhancing, and debugging the VHDL/Verifog for the chip.
• This includes verifying the functionality of the design on an HDL simulator (such as Model Sim or Xcelium) and synthesis with Synopsys or Genus.
• You will perform clock domain crossing (CDC) & reset domain crossing (RDC) verification, Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design.
• You will develop and port the RTL to an FPGA prototyping board.
• You will perform place and route of the netlist prior to tapeout, this includes clock tree synthesis (CTS).
• You will also run static timing analysis and power analysis after the CTS and place and route.
• Packaging and an evaluation board for the physical chip must also be performed.
• As an ASIC Design Engineer, you will develop and maintain technical procedures, documentation, and manuals and compile and analyze operational data and conduct tests to establish standards for new designs or modifications to existing equipment, systems, or processes.

• Bachelor degree in Hardware or Electrical Engineering (EE) with 8-10 years of experience, Masters degree in Hardware or Electrical Engineering (EE) with 6-8 years of experience or a PhD in Hardware or Electrical Engineering (EE) with 3-5 years of experience.
• Must be able to obtain and maintain a Secret clearance
• Minimum 3 years experience with targeting VHDL designs to Xilinx FPGA's
• Minimum 3 years experience using Cadence Virtuoso Minimum 5 years experience developing in VHDL and Verilog (or system Verilog)
• Minimum 3 years experience using Model Sim/Questa Sim

This is the projected compensation range for this position. There are differentiating factors that can impact a final salary/hourly rate, including, but not limited to, Contract Wage Determination, relevant work experience, skills and competencies that align to the specified role, geographic location (for Remote Opportunities), education and certifications as well as Federal Government Contract Labor categories. In addition, Arcfield invests in its employees beyond just compensation.

Arcfield ’s benefits offerings include, dependent upon position, Health Insurance, Life Insurance, Paid Time Off, Holiday Pay, Short Term and Long-Term Disability, Retirement and Savings, Learning and Development opportunities, wellness programs as well as other optional benefit elections. Min: $ Max: $

We are an equal opportunity employer and federal government contractor. We do not discriminate against any employee or applicant for employment as protected by law.