HSIO Electrical Validation Engineer

What You Do At AMD Changes Everything

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture.

We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

We are seeking a highly motivated DCGPU HSIO Electrical Validation Engineer to drive post-silicon electrical validation for high-speed interfaces in AMD data center GPU platforms. This role focuses on validating and enabling HSIO technologies such as PCIe, xGMI, UCIe, IFOE, and related high-speed PHY/interface paths across silicon bring-up, debug, compliance, manufacturing readiness, and product execution.

The engineer will work cross-functionally with design, architecture, signal integrity, package/board, firmware/software, quality, and system/platform teams to develop validation strategies, execute test plans, debug electrical issues, and improve validation coverage and methodology.

This role is ideal for an engineer who enjoys deep technical debugging, lab-based validation, high-speed interfaces, and solving difficult cross-functional problems. The most successful candidates combine strong electrical fundamentals, disciplined execution, and the ability to translate ambiguous failures into structured technical actions.

• Own and execute electrical validation for DCGPU HSIO interfaces across bring-up, characterization, debug, and product readiness phases.
• Develop, refine, and execute test plans, test methodologies, and validation coverage for high-speed interfaces and associated PHY behavior.
• Drive post-silicon validation activities from power-on and bring-up through product launch, including issue reproduction, root cause analysis, and closure.
• Perform and interpret lab measurements using high-speed electrical validation equipment such as oscilloscopes, BERTs, VNAs, and other protocol/electrical instrumentation.
• Correlate lab results with specification targets, simulation expectations, board/layout considerations, and silicon behavior.
• Partner with cross-functional teams to review board design, layout, channel conditions, fixture readiness, and test setup quality to ensure robust validation results.
• Identify gaps in validation coverage and improve effectiveness through automation, scripts, debug collateral, and reusable methodology.
• Support compliance/certification readiness and alignment with external lab or ecosystem expectations where applicable.
• Document validation procedures, execution results, key findings, debug learnings, and recommendations in a clear and scalable manner.
• Contribute to manufacturing/test readiness by supporting guard-banding, volume strategy inputs, debug methodology, and issue screening approaches where needed.
• Work closely with peers across functional validation, E2E validation, quality, and sustaining teams to ensure end-to-end product success.

• Experience in data center GPU, server platform, or HPC/AI system validation.
• Familiarity with board/layout review, fixture design considerations, simulation correlation, or compliance workflows.
• Experience in developing scalable test frameworks, debug tools, dashboards, or automation flows.
• Exposure to manufacturing validation, sustaining validation, or high-volume product readiness.
• Experience leading projects, driving cross-functional closure, or mentoring engineers.

• Electrical validation plans are comprehensive, executable, and aligned with product milestones.
• Key HSIO issues are debugged efficiently with clear technical root cause and corrective action.
• Validation coverage improves over time through better methodology, automation, and reuse.
• Cross-functional teams trust the engineer's technical judgment on interface readiness and risk.
• The engineer raises the quality, speed, and scalability of HSIO validation across current and future DCGPU programs.

Penang, Malaysia