Analog Layout Design Engineer

AMD Staff Analog Layout Design Engineer

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture.

We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

AMD is seeking an innovative Staff Analog Layout Design Engineer, working in collaboration with the circuit team for optimal planning and construction of the design. This is an opportunity to work with great people on leading edge technology that impacts the entire portfolio of products. Project tasks will include: floor-planning; power grid and signal flow planning; advanced transistor level layout; physical and electrical verification.

An experienced Analog Layout design engineer should be innovative, collaborative, meticulous, and curious.

Key responsibilities include:

• Complete layout design of analog, digital, and mixed signal circuits.
• Own major blocks of the custom IP designs.
• Direct/advise remote and local resources.
• Ensure all supplied data from resources are reviewed and meet milestone requirements.
• Schedule and forecast critical assigned blocks, maintaining schedule.
• Work closely with Engineering staff to ensure correct requirements are achieved.
• Working closely with Analog designers in floor planning; power grid and signal flow planning
• Physical and electrical verification include DRC, LVS, EM/IR, ERC, PERC Latch up and PERC ESD

Preferred experience includes:

• Knowledge of CMOS circuit theory.
• Ability to communicate with various teams to articulate specs and requirements as they pertain to layout
• Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools
• At least 8 years of relevant or comparable experience doing analog layout design
• Knowledge of chip level integration and ESD concepts a plus
• Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability
• Good understanding of signal and clock shielding and isolation techniques
• Ability to work well as part of a team

Academic credentials include:

Bachelor's degree in Engineering (or related field) OR Associates Degree in Engineering

Location:

Penang, Malaysia