Hardware Engineer, Design Verification

Requirements

• Experience:
  
  5+ years of experience in Digital Verification at a major semiconductor or EDA tool company
• Technical Stack:
  Advanced proficiency in System Verilog, UVM methodology, EDA verification tools (vManager, Xcelium, Jasper), and proficiency and application of Python or Perl scripting
• Domain Knowledge:
  Proven expertise in end-to-end design verification, including test plan creation, stimulus generation, and feature extraction
• Communication:
  Excellent written and spoken communication skills

• You will bring your expertise in the end-to-end design verification flow to support our Verification AI team. This is a hybrid verification and product-shaping role
• You will verify internal hardware (Physics inspired ASICs) while simultaneously reviewing the collateral generated by our AI to help refine product strategy and tool usability
• You will act as the bridge between raw verification data and our Machine Learning models, ensuring our AI learns from high-quality, curated, and synthesized data
• AI Product Refinement:
  Review AI-generated collateral to help shape product strategy and refine AI outputs in collaboration with the ML team
• Thermodynamic ASIC Verification:
  Provide design verification for internal hardware projects
• Tool Usability:
  Set up and evaluate EDA tools, ensuring internal tool usability and effective deployment on shared computing resources
• Testbench Development:
  Verification collateral development: create testbench environments, assertions, and coverage, from design documents, to support product development, functional coverage, and coverage closure
• Dataset Annotation:
  Curate and annotate datasets to make it easier to associate specific parts of a chip specification with specific test cases
• Quality Control:
  Establish rigorous quality criteria for verification data and implement continuous refinement processes
• Automated QA:
  Implement data augmentation methods and automated quality assurance checks to ensure high-fidelity data for ML training
• Synthetic Data Creation:
  Generate synthetic data using AI-based methods to supplement real datasets
• ML
  
  Collaboration:
  
  Collaborate with ML teams to ensure synthetic data effectively challenges verification models
• Pipeline Automation:
  Build automated pipelines to annotate test data and link it explicitly to chip specifications
• Document Parsing:
  Automate document parsing (e.g., datasheets, protocol specifications) for contextual tagging and traceability