Senior PCB Design Layout Engineer

Senior PCB Design Layout Engineer

Penguin Solutions is seeking a Senior PCB Design Layout Engineer to support the development of high-performance memory and advanced hardware products. This role focuses on complex PCB layout and design execution for high-speed digital, mixed-signal, and power applications, including memory modules, custom memory platforms, and advanced system-level designs.

The ideal candidate will have strong hands-on experience with Cadence Allegro and OrCAD Capture, high-speed routing, controlled impedance design, SI/PI design principles, HDI technologies, PCB stack-up development, power delivery considerations, and manufacturability requirements. This position requires close collaboration with hardware engineering, SI/PI, mechanical, manufacturing, test, fabrication, assembly, and customer-facing teams to deliver reliable and manufacturable designs from concept through production release.

Responsibilities include owning PCB design layout execution from initial floor planning through release to fabrication and assembly. Work closely with hardware engineers, SI/PI engineers, mechanical engineers, PCB designers, manufacturing, and test teams to design new products and modify or sustain existing products. Create PCB component footprints per applicable IPC standards and manufacturer data sheets, when needed. Create and review multilayer PCB stack-ups, including impedance-controlled, high-speed, mixed-signal, power, and HDI designs.

Define board outlines, mechanical constraints, placement keepouts, route keepouts, and other physical design requirements. Identify signal topologies and implement electrical constraints using Cadence Allegro Constraint Manager. Perform component placement and PCB routing, including differential pairs, controlled impedance lines, fine-pitch BGA escape routing, and tight length-matching requirements. Define and implement high-speed PCB design constraints for DDR, PCIe, CXL, and other high-speed interfaces.

Work with SI/PI engineers to support signal integrity, power integrity, stack-up definition, impedance control, routing strategies, return-path planning, and crosstalk mitigation. Support power delivery network design through power plane planning, decoupling strategy, and PDN-aware placement and routing. Collaborate with PCB fabricators on stack-up, material selection, impedance targets, HDI construction, DFM, yield, cost, and schedule tradeoffs. Prepare fabrication drawings, assembly drawings, Gerber files, ODB++/IPC-2581 files as required, and complete PCB release packages.

Lead placement reviews, routing reviews, post-layout reviews, and DFM reviews, and support schematic and manufacturing readiness reviews. Mentor junior PCB designers and help improve PCB design standards, library practices, constraint methodology, and release processes. Stay current with industry standards, PCB fabrication technologies, design tools, and best practices, and recommend improvements where appropriate.

Qualifications include a Bachelor's degree in Electrical Engineering, Electronics, or related technical discipline preferred; equivalent experience will be considered. Master's degree is a plus. 8+ years of PCB design/layout experience for high-speed digital, mixed-signal, and power designs. 5+ years of hands-on experience with Cadence Allegro and OrCAD Capture. Strong experience with high-speed digital design practices, controlled impedance routing, differential pair routing, length matching, timing/skew management, topology implementation, return paths, and crosstalk considerations.

Experience with complex multilayer PCBs, preferably 12-24+ layers, including HDI, blind/buried vias, microvias, via-in-pad, sequential lamination, fine-pitch BGAs, and advanced fabrication constraints. Experience with power supply circuits, analog circuits, mixed-signal layout practices, and power delivery considerations. Ability to read, interpret, and apply component manufacturer data sheets, reference designs, layout guidelines, and fabrication requirements. Working knowledge of JEDEC DDR4 and DDR5 standards is highly preferred.

Experience with DDR3, MRDIMM, CXL, PCIe, or other high-speed memory interfaces is a plus. Experience designing memory modules, server boards, accelerator cards, storage products, or high-speed embedded systems is a plus. Ability to interface with customers and internal stakeholders to understand requirements and translate them into manufacturable PCB designs. Self-starter with strong organizational skills, attention to detail, ownership mindset, and excellent verbal and written communication skills.

Ability to identify areas of innovation in memory design. Experience with invention disclosure or patent processes is a plus.

This position can sit remotely in the Pacific Time Zone, with preference being in the state of California. There are physical locations in Newark, CA and Irvine, CA should you prefer a Hybrid or Onsite model. Travel None anticipated Compensation & Benefits…