Physical Design Engineer, HBM

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Micron’s High‑Bandwidth Memory (HBM) Digital Design organization is seeking a Digital Physical Design Engineer to drive backend implementation of high‑performance, low‑power digital logic used in advanced memory products. This role spans backend implementation from Netlist to GDSII, with a strong focus on timing closure, power integrity, and manufacturability in advanced process technologies. The successful candidate will work closely with RTL, DFT, CAD, and verification teams to deliver high‑quality physical designs, contribute to methodology improvements, and help push performance, power, and area (PPA) targets in complex, multi‑hierarchy designs.

• Own and execute physical design implementation from synthesized netlist through GDSII, including floor planning, placement, clock tree synthesis, routing, and physical signoff
• Utilize AI-Enabled tools in the Netlist to GDS flow
• Perform and drive timing closure across multiple modes, corners, and scenarios using industry‑standard STA tools
• Analyze and resolve congestion, timing, IR drop, EM, and power integrity issues
• Develop and refine floor plans, power grids, and clocking strategies for high‑performance designs
• Work with placement and timing closure of custom analog hard IP macros in a digital‑on‑top design flow
• Collaborate closely with RTL designers to influence partitioning, constraints, and micro‑architecture decisions early in the design cycle
• Implement and validate low‑power design techniques, including multiple/isolated power domains, power gating, and UPF/CPF‑based power intent
• Execute physical verification (DRC/LVS/ANT/DFM) and support signoff flows
• Drive functional and timing ECOs as needed to meet design targets
• Use scripting and automation (TCL, Python, etc.) to improve productivity, quality, and flow robustness
• Interface with EDA vendors and internal CAD teams to debug tool issues, evaluate new tools and functions, and improve physical design methodologies.

• Strong understanding of the RTL‑to‑GDSII physical design flow particularly floor planning, place & route, clock distribution, and timing analysis and closure using standard EDA tools and advanced process technologies
• Experience with full‑chip integration, partitioning, and budgeting
• Solid understanding of power, performance, and area tradeoffs
• Knowledge of low‑power architectures, including DVFS, power gating, and multi‑voltage designs
• Proficiency in scripting/programming (TCL , Python, Perl, Shell scripting)
• Strong problem‑solving skills and ability to debug complex physical design issues
• Effective communication skills and ability to work in a cross‑functional team environment
• Experience in validating Power Distribution Network (PDN), IR/EM

• Experience with advanced technology nodes
• Experience with high‑frequency, high‑density designs and complex clocking schemes
• Familiarity with memory, HBM, or datapath‑intensive designs
• Understanding of device physics and process‑technology impacts
• Experience in the 3D-IC technology, methodology, and advanced packaging and thermal considerations

• Required:
  
  Bachelor’s degree in EE with good understanding of computer architecture and 7+ years experience in related field
• Desired:
  Master’s degree in EE / CE with 5+ years experience in related field

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