ASIC​/FPGA Design Verification Engineer

Our Purpose

TERADYNE's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought in our workforce. Our employees are supported to innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation, and delivers better business results.

Our Logic Design Engineering (LDE) team is seeking a Digital Logic Verification Engineer, preferably with additional experience in FPGA design. The primary focus of this role is FPGA verification, working closely with cross‑functional teams to deliver high‑quality, robust designs.

• Review design requirements and specifications
• Write and review verification plans
• Develop testbench architecture and implementation
• Create reference models
• Write System Verilog tests and develop UVM environments; perform debug
• Collect, merge, and close functional and code coverage
• Manage bugs and issues using a tracking tool
• Collaborate closely with logic designers
• Communicate technical status and risks to the team leader

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us on this mission, take a closer look at the minimum criteria for the position.

• 5+ years of professional experience in digital logic verification or related roles
• Experience with Cadence Xcelium or other industry‑standard simulators
• Strong experience with System Verilog and Universal Verification Methodology (UVM)
• Working knowledge of common IP protocols (e.g., SPI, AXI, DDR)
• Experience with RTL design using Verilog HDL
• Familiarity with System Verilog assertion‑based verification methodologies
• Experience working within CI/CD development flows

This position is located at our North Reading, MA development center.

This position is not eligible for visa sponsorship.

The base salary range for this role is $123,100 - $196,900. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

This job is eligible for discretionary bonus(es) based on financial performance.

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please  to see details.