ASIC and Logic Design Engineering Manager; Compute Test, North Reading

ASIC And Logic Design Engineering Manager (Compute Test, North Reading)

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Opportunity Overview:
The Logic Design Manager is responsible for leading a team of developers in designing and verifying FPGA's for Teradyne Compute Test Division's next generation products. In this role you will lead a team of ~4-6 engineers in a fast-paced environment to help the organization meet key business needs. Requires close collaboration with the other FPGA design and verification managers and with other engineering disciplines including mixed signal ASIC design, circuit board design, software and systems engineering to specify and implement new products.

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About You:

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you're ready to join us in this mission, take a closer look at the minimum criteria for the position. BSEE or MSEE and 12+ years of relevant experience in Digital FPGA design and integration (Digital ASIC experience is a plus).

Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects from concept, architecture exploration, design implementation and lab validation to production release. Extensive experience coding RTL (verilog preferred). Extensive experience using digital simulation tools (Cadence preferred). Extensive experience using static timing analysis tools. Experience designing with the following: PCIe, DDR3/4/5, AXI, ethernet, SPI, SERDES Experience with either AMD or Altera FPGAs and development tools (Vivado/Quartus), preferably both.

Experience using digital design quality tools e.g. LINT, CDC. Experience with bug tracking tools (Jira etc.) Experience with source control systems (Clearcase, Git, CVS) and continuous integration. Familiarity with digital verification tools and methodologies (preferably UVM). Experience with project scheduling tools (e.g. Microsoft project) Experience with embedded processors and digital signal processing is a plus. Experience with high level programming languages (C, C++) is a plus.

Excellent presentation and communication skills.

Compensation:
The base salary range for this role is $155,500 - $ 248,700. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location. Incentive Plan:
This job is eligible for discretionary bonus(es) based on financial performance. Benefits:
Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.