ASIC​/FPGA Design Verification Engineer

Digital Logic Verification Engineer

Required

Skills & Experience:

• 5+ years of professional experience in digital logic verification or related roles
• Experience with Cadence Xcelium or other industry-standard simulators
• Strong experience with System Verilog and Universal Verification Methodology (UVM)
• Working knowledge of common IP protocols (e.g., SPI, AXI, DDR)
• Experience with RTL design using Verilog HDL
• Familiarity with System Verilog assertion-based verification methodologies
• Nice to Have
  
  Skills & Experience:
• Experience working within CI/CD development flows

Job Description:

Our Logic Design Engineering (LDE) team is seeking a Digital Logic Verification Engineer, preferably with additional experience in FPGA design. The primary focus of this role is FPGA verification, working closely with cross-functional teams to deliver high-quality, robust designs.

In this role, you will:

• Review design requirements and specifications
• Write and review verification plans
• Develop testbench architecture and implementation
• Create reference models
• Write System Verilog tests and develop UVM environments; perform debug
• Collect, merge, and close functional and code coverage
• Manage bugs and issues using a tracking tool
• Collaborate closely with logic designers
• Communicate technical status and risks to the team leader