Memory Layout Engineer; Germany

Experience: 5–7 Years

Location: Germany

Domain: Semiconductor / Memory Design

We are looking for a Memory Layout Engineer with 5–7 years of hands‑on experience in memory layout design
, specifically on lower technology nodes
. The role involves layout development, verification, and close collaboration with design and verification teams.

• Perform memory layout design for SRAM / memory blocks

• Work on lower technology nodes (mandatory)

• Ensure layout meets DRC, LVS, and density requirements

• Optimize layout for performance, power, and area (PPA)

• Collaborate with circuit design and verification teams

• Support tape‑out activities and resolve layout‑related issues

• 5–7 years of experience in memory layout engineering

• Strong experience in lower nodes (mandatory)

• Hands‑on with DRC/LVS closure

• Good understanding of semiconductor layout fundamentals

• Experience with advanced memory architectures
• Exposure to multiple process nodes
• Strong communication and teamwork skills