Senior ASIC Power Engineer – AR​/VR Silicon | Remote

Position: Design Engineer V (ASIC Power Engineer)

Type: Full-Time

Compensation: $100–$135/hour

Location: Sunnyvale, CA, United States

• Perform Power, Performance, and Area (PPA) optimization using Synopsys Fusion Compiler.
• Conduct RTL and netlist‑level power analysis for ASIC designs supporting AR/VR products.
• Develop scripts and post‑processing tools to analyze report log files, perform format conversions, and extract relevant design insights.
• Setup, run, debug, and analyze reports across ASIC design flows including synthesis, physical design, power, and timing.
• Implement selected design blocks at RTL and power intent using UPF.
• Document workflows, methodologies, and analysis results clearly for cross‑functional teams.

• Strong experience as an ASIC Power Engineer, CAD Engineer, or Physical Design Engineer.
• Experience with power estimation tools, synthesis workflows, and aspects of physical design.
• Strong understanding of power trade‑offs in chip design and back‑end implementation.
• Hands‑on experience with scripting and data analysis tools.
• Proficiency with Python, Tcl, and System Verilog.
• Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent experience.

• Upload resume
• Interview
• Submit form