SW Engineer Layout Design 3D-IC Solutions

SW Engineer Package Layout Design 3D-IC Solutions

Job

Posted since: 29-Apr-2026

Organization:
Siemens Industry Software Inc.

Field of work:
Research & Development

Job type:
Full-time, Hybrid (Remote/Office), Permanent

Locations:

• Santa Clara, California, United States of America
• Wilsonville, Oregon, United States of America

Siemens EDA is a global technology leader in Electronic Design Automation (EDA) software. As a Software Engineer, you will contribute to developing innovative software products and comprehensive workflow solutions for advanced 2.5D and 3D System-in-Package (SIP) designs. Your role involves integrating Siemens’ industry‑leading EDA and MCAD tools to facilitate architectural planning, physical design/verification, multi‑die analysis, and manufacturing test, impacting the future of chip design.

• Drive the integration and seamless workflow between physical design and 3D‑IC planning tools for complex, multi‑die advanced packaging designs.
• Develop, document, and champion methodologies for constructing chiplet designs within physical implementation environments and effectively integrating them into 3D‑IC planning platforms.
• Create and integrate substrate/package designs using advanced package layout tools, ensuring smooth transfer and assembly within 3D‑IC planning environments.
• Perform complex 3D assembly of chiplets and packages within 3D‑IC planning tools and execute comprehensive verification to ensure LVS (Layout Versus Schematic) and DRC (Design Rule Check) cleanliness.
• Develop robust scripts and automation solutions using Python, Tcl/Tk, Bash, or similar languages to enhance design efficiency, streamline workflows, and improve tool interoperability.
• Act as a technical expert, providing guidance, support, and best practices to internal teams and potentially key customers. This includes understanding user needs, demonstrating solutions, and contributing to technical documentation.
• Diagnose and resolve complex technical issues related to tool integration, advanced packaging methodologies, and verification challenges.
• Keep abreast of the latest advancements in advanced packaging, 3D‑IC technologies, and explore the application of Artificial Intelligence (AI) to optimize design flows and verification processes.

• Master’s degree in electrical engineering, Computer Engineering, or a closely related technical field with 5+ years of relevant industry experience.
• Demonstrated hands‑on expertise with advanced packaging design tools, including a strong working knowledge of building 3D packages.
• Proficiency in scripting and software development using Python, Tcl/Tk, Bash, or similar languages for automation and workflow customization.
• Strong understanding of advanced packaging design principles and methodologies.
• Experience with industry‑leading physical implementation/Place & Route tools and 3D‑IC planning/integration tools.
• Working knowledge of advanced package layout design tools (e.g., for substrate/package design).
• Familiarity with 3D verification tools for LVS and DRC in 3D‑IC environments.
• Strong problem‑solving abilities and a proactive approach to identifying and resolving technical challenges.
• Excellent communication skills, both written and verbal, with the ability to articulate complex technical concepts to diverse audiences.
• Ability to work independently and collaboratively in a fast‑paced, dynamic environment.

• Direct experience with Package Design tools (e.g., Cadence APD/SiP, Siemens Xpedition) and Package / Interposer planning solutions (e.g., Siemens Innovator 3D IC, Cadence Integrity/Innovus, Synopsys 3
  
  DIC Compiler).
• Familiarity with the application of Artificial Intelligence (AI) in EDA workflows, particularly in areas like design optimization, verification, or methodology development.
• Knowledge of advanced process nodes and their implications for advanced packaging.
• Familiarity with IC analysis tools such as Siemens Hyper Lynx, Ansys HFSS and Redhawk, Cadence Voltus, or Synopsys Prime Time for signal and power integrity analysis in physical design.
• Understanding of multi‑physics analysis relevant to advanced packaging, including signal integrity…