MTS Digital Engineering

Overview

As a New College Graduate Design Engineer, the full-time position candidate will be responsible for specifying, architecting, implementing, and simulating RTL components. The individual will work closely with specification developers, digital & analog designers, and physical design teams to realize efficient and highest performance designs. The position is for DDR5 and DDR6 enterprise-class memory interface products to grow the Memory Interface Chip Business Unit.

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.

• Develop system Verilog RTL IP, logic, and state machines for next generation products
• Perform block level design integration and block level simulations to qualify behavior
• Document design implementation with descriptions and functional diagrams
• Estimate and track power, performance, area (PPA) tradeoffs for RTL designs
• Collaborate with design team members individually and in group meetings to track status and ensure design implementation achieves desired outcomes
• Review and improve Static Timing Analysis (STA) results
• Creating Verilog functional models to be used in simulations
• Work closely with verification team to debug verification results
• Support validation team during chip power-on and debug efforts
• Perform design quality checks with CDC/RDC/LINT tools

• BS in Electrical Engineering with 2-3 years experience, or MS in Electrical Engineering or Computer Engineering with 0-1 year of experience
• Coursework:
  Digital Integrated Circuits, Advanced VLSI Systems, Advanced Computer Architecture, Embedded Systems, Design and Analysis of Algorithms, Fundamentals of Machine Learning
• Background in Digital RTL design including standard LEC, CDC, Lint, DFT, BIST, STA tools
• High aptitude with Verilog and System Verilog
• Ability to document design techniques, test, and verification methodology.
• Python/perl script development
• Interface with debug, test, product, and reliability engineers for product qualification

The US salary range for this full-time position is $58,000 to $108,000. Our salary ranges are determined by role, level and location. The successful candidate’s starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.

Rambus is proud to be an Equal Employment Opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application.