Senior FPGA Verification Architect; UVM, Remote

QuEST Defense is hiring a Senior FPGA Verification Engineer in remote capacity to lead the design of UVM-based verification environments. Your role involves hands-on leadership in developing strategies for verification, mentoring engineers, and ensuring high-quality FPGA designs in mission-critical applications.

With responsibilities including defining test plans and driving coverage closure, you bring over 8 years of experience in FPGA/ASIC verification and a strong command of System Verilog and UVM. Competitive compensation of $150,000 to $180,000 annually is offered.