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Senior Physical Design Engineer; remote at Chelsea Search Group Richardson, TX

Remote / Online - Candidates ideally in
Richardson, Dallas County, Texas, 75080, USA
Listing for: Feitong Buke
Full Time, Remote/Work from Home position
Listed on 2026-05-26
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Electrical Engineering, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 110000 - 140000 USD Yearly USD 110000.00 140000.00 YEAR
Job Description & How to Apply Below
Position: Senior Physical Design Engineer (remote) at Chelsea Search Group Richardson, TX

Senior Physical Design Engineer

Remote location possible. Richardson, TX (onsite/hybrid) or remote.

Contract (6+ months with possible extensions).

US Citizen or US Permanent Resident required.

Responsibilities
  • Architect system requirements
  • Collaborate effectively with the full ASIC design implementation team with a humble, hungry and smart attitude
  • Leverage or enhance existing digital design flow and solve design and flow issues within Cadence Genus, Innovus, Tempus
  • Plan budget, tools and team effort and champion project needs to ensure milestones and objectives are met
  • Super user of industry standard Physical Design, Synthesis and Timing Analysis tools
  • Accountable for physical design implementation of complex, low‑power designs including physically aware logic synthesis, DFT, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification
Skills / Experience
  • BSEE/MSEE with 5+ years of related industry experience
  • 5+ years hands‑on experience in high reliability, low power VLSI designs
  • 5+ years of experience with Cadence digital design tools (Genus, Innovus, Tempus)
  • Basic proficiency with programming languages such as Perl, C and TCL
  • Excellent understanding of reliability, test and power concepts & design tradeoffs required
  • ITAR compliance approval required
  • Knowledge of MIPI, I2S, CAN protocols a plus
  • Skilled with Verilog/VHDL RTL and able to modify for timing or power closure
  • Production‑proven experience with floor planning at chip level with Bus/Pin variables, synthesis, place and route optimization, parasitic extraction, static timing analysis, low power intent (UPF/CPF), power analysis, IR drop analysis, electromigration, physical verification and sign off
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Position Requirements
10+ Years work experience
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