Senior ASIC Verification Architect - Remote

Palo Alto Networks Unit 42 is seeking a Sr ASIC Design Verification Engineer based in Santa Clara, California. The candidate will be responsible for ensuring that ASICs meet industry-leading standards for next-generation firewall products by defining methodologies, architecting test benches, and writing tests.

This role requires expertise in System Verilog, UVM, and a minimum of 5 years of experience in ASIC Design Verification. Ideal candidates are expected to collaborate effectively with diverse teams and demonstrate strong leadership skills.