Principal Mixed Signal Architect

Application close date:

Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We're working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!

We are seeking a Principal Mixed-Signal Architect to lead the definition and development of high-performance mixed-signal subsystems for advanced communication and data-conversion SoCs. This role will own architecture, top-level specifications, behavioral modeling, IP strategy, and cross‑functional integration for critical mixed‑signal building blocks such as Ser Des, ADCs, PLLs, VGAs, TIAs, and quantize rs. The ideal candidate brings deep expertise in high‑speed mixed‑signal IC design, strong system‑level insight, and a proven track record delivering complex products in advanced process nodes.

• Relocation provided
• Travel expected up to 15% of the time
• This role is open to Seattle, Bay, San Diego and Austin Areas. A temporary remote work exception will be made for certain locations as we finalize our office spaces in the area.

• Own top-level specifications for mixed‑signal subsystems, including:
• Link budgets for Ser Des (PAM4/NRZ)
• ENOB/SNDR targets for high‑speed ADCs
• Develop high‑level behavioral models in MATLAB, Simulink, or System Verilog-AMS to validate system performance before circuit implementation
• Evaluate make‑versus‑buy decisions for Ser Des and ADC IP and recommend the best technical and business path.
• For internally developed solutions, lead circuit architecture and design implementation of key analog/mixed‑signal blocks such as PLLs, VGAs, TIAs, and quantize rs
• Define calibration and adaptation algorithms, including FFE, DFE, and adaptive gain control
  , that are implemented in RTL and used to optimize analog block performance
• Partner with packaging and physical design teams to define pinouts, bump maps, guard rings, and isolation strategies that minimize noise coupling between high‑speed analog and noisy digital logic
• Drive cross‑functional architecture tradeoffs across analog, digital, packaging, and system teams
• Lead post‑silicon validation of mixed‑signal subsystems in the lab using high‑speed test equipment such as oscilloscopes and BERTs
• Support debug, characterization, and performance correlation between simulation and silicon results.
• Provide technical leadership and mentorship across mixed‑signal architecture and design activities.

• Bachelor of Sciences Degree in Electrical Engineering with a focus on Analog/Mixed‑Signal design
  .
• 15+ years of experience in mixed‑signal IC design.
• Proven track record delivering high‑speed Ser Des (16G/32G/56G/112G) and high‑speed ADCs such as SAR, Pipeline, or Sigma‑Delta architectures.
• Deep experience in advanced FinFET process nodes (7nm, 5nm, or below).
• Strong layout‑dependent effects (LDE) management, electromigration, and other advanced‑node implementation challenges.
• Expert knowledge of industry‑standard design and simulation tools including Cadence Virtuoso, Spectre/HSPICE, and AMS Designer
  .
• Strong understanding of mixed‑signal system architecture, performance tradeoffs, and silicon validation.
• Experience working across architecture, circuit design, RTL, packaging, and lab validation teams.

• MS or PhD in Electrical Engineering with a focus on Analog/Mixed‑Signal design
  .
• Familiarity with EM simulation tools such as EMX or Ansys
  .
• Understanding of high‑speed interface and networking protocols such as PCIe Gen5/Gen6 and Ethernet
  .
• Experience defining calibration, adaptation, and equalization schemes for high‑speed links and data converters.
• Background in system modeling and architecture evaluation for communications or sensor‑interface applications.
• Experience partnering with packaging teams on signal integrity, substrate noise, and high‑speed integration challenges.
• Strong lab bring‑up and post‑silicon debug experience for mixed‑signal silicon.

Compens…