Digital Verification Engineer - Weapon Subsystems

What Your Job Will Be Like

Sandia National Laboratories is seeking a Digital Verification Engineer (R&D Electrical Engineer) with expertise in formal verification tools to ensure the correct functionality of ASIC and FPGA designs. The ideal candidate will have hands‑on experience with VHDL and Verilog design languages and be proficient in using System Verilog Assertions (SVA) within formal verification environments.

Success in this role requires a strong foundation in digital design principles, a detail‑oriented and logical approach to problem‑solving, and excellent written communication skills.

As a Digital Verification Engineer, you will:

• Translate digital design requirements at various development stages into precise, unambiguous checks against the implementation.
• Adapt diverse requirements—including functionality, safety, and information protection—into System Verilog Assertions (SVA) for verification.
• Evaluate trade‑offs in formal analysis complexity to ensure verification tasks remain tractable and efficient.
• Collaborate closely with designers, system engineers, and other verification specialists to deploy systems that are verifiably correct.
• Produce clear, concise, and well‑documented archival reports detailing verification activities and results.
• Present verification findings at technical reviews to peers and customers.
• Continuously learn and apply new formal verification techniques and methodologies.

While this position is ideally based on‑site in California or New Mexico with hybrid flexibility, remote work from any U.S. state may be considered. Candidates working remotely must be able to travel to the California site approximately once per month to support mission needs.

Applicants on this requisition may be interviewed by multiple organizations at Sandia National Laboratories.

$121,900 - $237,800

Salary range is estimated, and actual salary will be determined after consideration of the selected candidate's experience and qualifications, and application of any approved geographic salary differential.

• A Bachelor's degree in a relevant discipline, or an equivalent combination of directly relevant education and engineering or scientific experience that demonstrates the knowledge, skills, and ability to perform independent research and development.
• Ability to obtain and maintain a DOE Q-level security clearance.

• Graduate degree in Electrical Engineering or a highly related field where an independent research project was a graduation requirement (e.g., independent project, thesis, or dissertation).
• Ability to work independently and collaborate well in a multidisciplinary team of designers and test engineers.
• Outstanding verbal and written skills, including the ability to develop and present briefings that are clear and compelling.
• Several years of experience applying formal verification techniques to FPGA or ASIC designs.
• Proficiency with VHDL, Verilog, and System Verilog Assertions (SVA).
• Strong analytical skills with meticulous attention to detail in both technical work and documentation.

Sandia is required by DOE to conduct a pre‑employment drug test and background review that includes checks of personal references, credit, law enforcement records, and employment/education verifications. Applicants for employment need to be able to obtain and maintain a DOE Q-level security clearance, which requires U.S. citizenship. If you hold more than one citizenship (i.e., of the U.S. and another country), your ability to obtain a security clearance may be impacted.

Applicants offered employment with Sandia are subject to a federal background investigation to meet the requirements for access to classified information or matter if the duties of the position require a DOE security clearance. Substance abuse or illegal drug use, falsification of information, criminal activity, serious misconduct or other indicators of untrustworthiness can cause a clearance to be denied or terminated by DOE, resulting in the inability to perform the duties assigned and subsequent termination of employment.

All qualified applicants will receive…