Senior Design Verification Engineer

Senior Design Verification Engineer

Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you.

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span from projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC products for vision processing, aerospace FPGAs, medical electronics, RISC-V based SoC, ARM based peripherals, and mixed signal DSPs. Successful candidates for this role will support verification of advanced CPU/GPU based SOCs.

Correct Designs is NOT the typical contracting, staff augmentation firm. Our engineers have respected long term roles with generous hourly rates in excellent team environments. A typical contract may last 3 years, although we have shorter and even longer term work available. We are well respected in the Design Verification community with clients always seeking new CDI engineers. If you need a few months off between contracts you can take that break and know there will be plenty of work available when you return.

If you like the stability of always working, simply move to the next contract with little time off. Correct Designs does provide health care and retirement plan benefits.

We are based in Austin, Texas with clients throughout the US. There are opportunities for both in-person and remote work.

Our current positions are filled but we have clients looking for skilled CDI engineers on a regular basis. Please submit your resume so we can match you up with upcoming projects. Whether you are an experienced veteran looking for new challenges, or a talented engineer seeking to broaden your experience, we can offer exciting options for your career. Correct Designs uses E-Verify to confirm work status eligibility.

Responsibilities:

• Verify complex design blocks using equally complex SV/UVM verification environments
• Develop and execute pre-silicon verification test plans
• Develop directed and random verification tests to validate block and IP functionality
• Develop verification components and tools
• Develop verification functional coverage using industry standard coverage analysis tools/methods
• Debug regression fails
• Replicate functional issues found in external environments or post-silicon; review/enhance tests to verify bug fixes

Required

Skills and Experience:

• 8 or more years of proven verification experience in a hardware development setting
• Strong background in System Verilog and UVM verification methodologies
• Strong debug skills and experience with debug tools such as DVE/Verdi
• Proficiency in Object Oriented programming, computer architecture and data structures
• Strong analytical/problem solving skills and pronounced attention to details
• Strong interpersonal and communication skills
• Must be comfortable working across geographies

Desired

Skills:

• Experience architecting/developing verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar
• Experience in other related domains such as formal verification, RTL design, or software development

Education:

Bachelor or Master's in Electrical Engineering, Computer Engineering, or Computer Science