Senior Silicon Physical Design Engineer - TeraWave

Senior Silicon Physical Design and Layout Engineer

Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low‑cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! Blue Origin is pioneering the future of space‑based communications with Tera Wave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth.

We are seeking a Senior Silicon Physical Design and Layout Engineer to design and develop advanced integrated circuits for our revolutionary space-based communications network. The ideal candidate brings expertise in physical design methodologies, layout techniques, and semiconductor technologies, thriving in a fast‑paced environment where innovation meets mission‑critical execution.

• Relocation provided
• Travel expected up to 10% of the time
• Interviews will include a technical assessment
• This role is based on site in Austin, TX;
  San Diego, CA; the Bay Area, CA; or Renton, WA. A temporary remote work exception is approved while our Bay Area, Austin, and/or San Diego sites are being developed.

• Execute physical design and layout of ASICs that integrate both analog and digital processing
• Implement floor planning, power distribution, clock tree synthesis, and routing for complex mixed‑signal designs
• Develop ASICs that meet the stringent standards of space qualification, ensuring high performance and efficiency
• Perform timing closure, signal integrity analysis, and physical verification (DRC/LVS/ERC)
• Implement advanced RF processing technologies that support missions with reduced size, weight, and power (SWaP)
• Optimize layouts for radiation tolerance and reliability in the space environment
• Collaborate with front‑end designers to ensure design intent is preserved through implementation
• Perform static timing analysis and address timing violations
• Utilize data analytics to optimize ASIC performance and drive innovation
• Work with semiconductor foundries to ensure manufacturability and yield optimization
• Implement design for test (DFT) structures and methodologies
• Document physical design processes, methodologies, and results
• Support post‑silicon validation and debug activities

• B.S. degree in Electrical Engineering, Computer Engineering, or related field
• 7+ years of experience in physical design and layout of ASICs
• Demonstrated expertise in digital and analog layout techniques
• Experience with industry‑standard EDA tools for physical design (Cadence, Synopsys, or Mentor)
• Knowledge of semiconductor fabrication processes and design rules
• Understanding of timing closure and signal integrity challenges
• Experience with power analysis and optimization techniques

• Advanced degree (MS/PhD) in Electrical Engineering, Computer Engineering, or related field
• Experience with mixed‑signal or RF layout techniques
• Knowledge of radiation‑hardened design methodologies
• Experience with advanced process nodes (16nm and below)
• Background in high‑speed digital design (>1GHz)
• Experience with 3D packaging or chiplet technologies
• Understanding of thermal considerations in ASIC design
• Familiarity with space qualification requirements for electronic components
• Experience with low‑power design techniques for battery or solar‑powered systems

• California applicants: $ - $
• Washington applicants: $ - $

• Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long‑term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
• Stock Options for all regular employees (working at least 20 hours/week)
• Paid Time Off:
  Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company‑paid holidays.
• Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual…