ASIC Back-End​/Physical Design Engineer

RESQUANT is a rapidly growing deep-tech startup focused on next-generation chip security and quantum-resistant cryptography solutions. We are currently seeking experienced ASIC Back-End / Physical Design Engineers to join our team and contribute to the development of advanced hardware security technologies for high-security applications.

• Driving the full physical implementation flow, including floor planning, placement, clock tree synthesis, and routing for cryptographic processors.
• Performing timing closure and static timing analysis signoff across multiple corners and modes.
• Executing power planning and analysis, including IR-drop and electromigration checks.
• Implementing low-power architectures such as power domains, level shifters, and isolation cells.
• Managing synthesis-to-layout handoff, ECOs, and tapeout preparation in cooperation with the foundry.

• Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Over 5 years of hands-on experience in ASIC back-end or physical design.
• Proficiency with place-and-route tools such as Innovus or IC Compiler II.
• Strong static timing analysis skills and experience with signoff tools like Prime Time or Tempus.
• Experience with physical verification tools for DRC/LVS and knowledge of low-power implementation.
• EU citizenship and eligibility for employment under a Polish employment contract.

• Full-time employment contract with flexible working hours.
• Opportunity to work on cutting-edge projects in the field of chip security.
• Equity options and broad technical ownership.
• Fully remote work environment.
• Participation in innovative projects aimed at providing a backbone for chip security.