Hardware ASIC Packaging SI​/PI Simulation and Design Lead; Remote

The application window is expected to close on: 01/28/2027

This Hardware Engineering position is located in San Jose, CA, and is open to remote applicants residing within the United States.

Cisco Silicon One (#Cisco Silicon One ) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.

We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry!

We are seeking a highly qualified Signal and Power Integrity Technical Lead to help us develop our next generation ASIC packaging to help define, design and verify ASIC packaging to be deployed in a range of Cisco platforms.

• Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
• Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
• Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
• Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
• Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments.
• Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
• Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met.
• Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams.

• Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 6+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 3+ years of relevant signal and power integrity experience.
• High-Speed Design & Theory:
  Experience with high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 Ser Des architectures, channel modeling, and BER prediction.
• SI/PI Simulation Proficiency:
  Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
• Layout Review & Physical Validation:
  Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and crosstalk mitigation.
• Circuit…