AMS DV Engineer — Analog​/Mixed-Signal Verification & UVM

A technology company is seeking an Analog/Mixed-Signal Design Verification Engineer to contribute to the development of advanced models and verification processes in Oregon. Candidates should possess strong skills in System-Verilog coding and analog design practices. Key responsibilities include developing test benches, running simulations, and working closely with design teams to ensure functional specifications are met. This position offers an opportunity to influence design changes and work on complex mixed-signal designs.
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