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Senior CPU RTL Design Engineer

Job in Oregon, Dane County, Wisconsin, 53575, USA
Listing for: Jobtailor
Full Time position
Listed on 2026-07-20
Job specializations:
  • Engineering
    Systems Engineer, Hardware Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 140000 - 210000 USD Yearly USD 140000.00 210000.00 YEAR
Job Description & How to Apply Below

• Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs.

• Participates actively in the definition of architecture and microarchitecture features of the CPU being designed.

• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

• Provide technical leadership and support to the design team leadership including proposing creative, innovative methodology and process initiatives to consistently improve efficiency and quality.

• Work closely with architecture and backend teams and with other design teams towards achieving best-in-class products.

• Build a strong and technically vital organization. Cultivate and reinforce appropriate group values, norms and behaviors.

Requirements
  • Bachelor's degree in Computer Science, Electrical, Electronics, Engineering, or related field with 12+ years of work experience OR Master's degree in Computer Science, Electrical, Electronics, Engineering, or related field with 10+ years of work experience OR PhD in Computer Science, Electrical, Electronics, Engineering, or related field with 6+ years of work experience.
  • 6+ years of experience in silicon development in CPU microarchitecture and logic design.
  • 5+ years of experience in technical leadership including delivering successful IP Projects.
  • 6+ years of experience with Timing Closure, Power Convergence; integer and/or floating point, OOO execution, reservation station design.
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Position Requirements
10+ Years work experience
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