FPGA Design Engineer Lead

Job Description

FPGA Design Engineer Lead for the Programmable Logic Design organization within Missiles & Fire Control (MFC). The team defines the digital backbone of precision engagement aerospace and defense systems for the United States and allied militaries, delivering high‑performance FPGA/ASIC solutions that meet rigorous aerospace standards.

• Own end‑to‑end development of sophisticated FPGA/ASIC architectures, from requirements capture through production release.
• Define, design, verify, and implement logic using VHDL/Verilog in AMD Vivado, Intel Quartus, or equivalent tool chains.
• Conduct trade studies to select optimal devices, balancing logic utilization, power, thermal performance, cost, and risk.
• Create detailed requirements and interface control documents that guide cross‑functional teams.
• Build high‑coverage verification environments with UVM or comparable frameworks and generate comprehensive test plans.
• Support Design Assurance Reviews and ensure compliance with MFC engineering standards and aerospace design practices.
• Provide technical leadership, code‑review guidance, and mentorship to junior and peer engineers.
• Drive the Design Architecture Development process, manage schedule milestones, and mitigate technical risks.
• Manage configuration control and versioning in LM‑approved repositories (Git Lab, etc.) and maintain complete, traceable design documentation.
• Represent FPGA/ASIC engineering in cross‑functional technical meetings, risk assessments, schedule reviews, and customer‑facing engagements.

• Bachelor of Science in Electrical Engineering or a closely related STEM field from an accredited university;
  Master’s degree or PhD preferred.
• Proficiency in HDL programming with VHDL, Verilog, and/or System Verilog.
• Experience with multiple FPGA vendors (Xilinx/AMD, Altera/Intel, Micro Semi/Microchip) and their part families, internal fabric, and IP.
• Experience with FPGA simulation tools such as Synopsys VCS and verification methodologies (UVM).
• Experience with version control systems such as Git/Git Lab.
• Must be a US Citizen and able to obtain a DoD Secret clearance.

• Experience with Xilinx/AMD FPGAs (including Versal) and related toolsets (Vivado, Vitis, Vitis HLS).
• Strong understanding of digital design principles, including timing analysis, clock‑domain crossing, and signal integrity.
• Experience in hardware‑software integration and validation.
• Experience with high‑speed data and memory interface implementation.
• LM/MFC design experience and missile/sensor program experience.
• Experience with the MFC Design Assurance / DAR process.
• Experience with safety boards and range safety requirements (RCC 319, MIL‑STD‑1316, JOTP‑051, MIL‑STD‑1901).
• Experience with System Verilog, Verilog, C/C++, MATLAB/Simulink;
  Synopsys Synplify, Synopsys VCS, NCSim, Chip Scope tool sets.
• Experience with Simulink and HDL Coder for model‑based FPGA design.
• Experience with EOIR imaging processing techniques and missile/processor interfaces.
• Proven ability to collaborate effectively with cross‑functional software, hardware, and systems engineering teams.
• Experience with full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test).

Secret clearance required. Must be a US Citizen with or eligible for a DoD Secret clearance.

Location:

Orlando, Florida.

Work schedule:

4×10 hour day, 3 days off per week. Part‑time remote telework is possible; the specific weekly schedule will be discussed during the hiring process.

Lockheed Martin is an equal opportunity employer. Qualified candidates will be considered without regard to legally protected characteristics.

Experienced Professional

MISSILES AND FIRE CONTROL

Possible

Hardware Engineering

Full‑Time

First