ASIC & FPGA Design Engineer Sr

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* Description:

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* You will be the Senior ASIC & FPGA Design Engineer for the Multi Domain Missile Warning Payload team  Our team creates large format, high frame rate imaging sensor systems that provide survivability enhancing situational awareness for air, space and surface platforms

** What You Will Be Doing*
* As the Senior ASIC & FPGA Design Engineer you will work side by side with a PLD subject matter expert to architect, design and implement programmable logic solutions for the imaging sensor system  You will integrate hardware, develop test plans and verify performance on demanding space based platforms, contributing to a scalable, high performance missile warning payload  Your responsibilities will include:

- Define architecture and design specifications for programmable logic components, develop and document RTL  VHDL/Verilog/System Verilog  gate level designs that meet performance, power, and reliability requirements

- Create synthesis, place and route, and timing closure strategies to ensure deterministic operation

- Generate comprehensive test plans, simulation models, and verification environments  UVM, System

C, Python based test benches  to validate functional correctness and timing margins

- Work closely with systems, mechanical, and software teams to integrate ASIC/FPGA solutions into the missile warning payload, ensuring compliance with interface, mass, and volume constraints

- Contribute to the creation and maintenance of design documentation, configuration management files, and version controlled repositories  e g , Git

** Why Join Us*
* Do you want to be part of a company culture that empowers employees to think big, lead with a growth mindset, and make the impossible a reality? We provide the resources and give you the flexibility to enable inspiration and focus  If you have the passion and courage to dream big, work hard, and have fun doing what you love then we want to build a better tomorrow with you

We offer flexible work schedules to comprehensive benefits investing in your future and security, Learn more about Lockheed Martin's comprehensive benefits package here

** Further Information About This Opportunity:*
* This position is in Orlando  Discover more about our Orlando, Florida location

MUST BE A U S  CITIZEN   This position is located at a facility that requires special access  The selected candidate must be able to obtain a secret clearance  A company sponsored Interim Secret is required to start

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* Basic Qualifications:

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* + Bachelor's degree or higher in Electrical or Computer Engineering

+ Relevant experience with FPGA design and simulation verification

+ Minimum 2 years with Xilinx/AMD Vitis and Vivado toolsets

+ At least 2 years of hands‑on experience using the Xilinx/AMD Ultra Scale design methodology

+ 2  years working with AXI, Ethernet, TCP/IP, and PCIe specifications

+ 2  years developing embedded C/C   applications using Xilinx/AMD Vitis

+ Minimum 2 years using Xilinx/AMD Vitis HLS tools

+ 2  years of coding in Verilog, System Verilog, or VHDL

+ At least 2 years of practical laboratory debug experience

+ 2  years operating high‑speed oscilloscopes, spectrum analyzers, and pulse generators

+ Minimum 2 years using Xilinx/AMD Vivado for FPGA debugging

+ 4  years of experience with Linux/UNIX, including writing shell scripts  BASH, csh , Perl, and/or Python

** Desired

Skills:

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* + Strong communications, collaboration, and presentation skills

+ LM design experience

+ Missile experience

+ MSEE or MSCE would be a plus

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Experience with System Verilog, Verilog, C/C  , MATLAB/Simulink, and System Verilog languages;
Synopsys Synplify, Synopsys VCS, NCSim, Chip Scope tool sets desired

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Experience with Xilinx/AMD and Micro Semi/Microchip part families, internal FPGA fabric and IP

+ FPGA design experience using the tools noted above

+ Previous experience related to aerospace design techniques would be a plus

+ Prior experience with Lockheed Martin MFC is a plus

+ Experience implementing NSA algorithms  e g , AES, counter mode, etc   

+ Experience managing configuration control  Git Lab preferred  

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Experience with Vivado and Vitis FPGA toolsets

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Experience with UVM

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Exp…