FPGA Engineer Lead

Job Description

You will be the FPGA Engineer Lead for the ATWS Directed Energy Imaging team. Our team delivers advanced imaging platforms by defining FPGA architectures, developing RTL, validating designs, and fielding production ready hardware that meets stringent performance, cost, and schedule goals.

What You Will Be Doing
As the FPGA Engineer Lead you will own the end to end development of FPGA solutions and coordinate a multidisciplinary group of systems engineers, software developers, and hardware integrators. You'll translate system requirements into reliable, high performance hardware while keeping technical risk in check and communicating progress to senior leadership and customers. Your responsibilities will include:

Defining FPGA architecture and creating high quality RTL using AMD/Xilinx Versal and Ultra Scale+ families.
Driving verification and validation activities, including board level testing and video/signal processing implementation.
Managing task assignments, configuration baselines, and version control (Git Lab) to ensure a smooth development flow.
Monitoring technical risks, updating schedules, and delivering status briefings that influence program decisions.
Producing production ready design packages-schematics, constraints, test reports, and bill of materials-for seamless hand off to manufacturing.
Collaborating with cross functional partners to align FPGA work with overall system architecture and mission objectives.
Guiding junior engineers, fostering a culture of technical excellence, and championing best practice design standards.

Why Join Us
Do you want to be part of a company culture that empowers employees to think big, lead with a growth mindset, and make the impossible a reality? We provide the resources and give you the flexibility to enable inspiration and focus. If you have the passion and courage to dream big, work hard, and have fun doing what you love then we want to build a better tomorrow with you.

We offer flexible work schedules to comprehensive benefits investing in your future and security, Learn more about Lockheed Martin's comprehensive benefits package here.

Further Information About This Opportunity:
This position is in Orlando. Discover more about our Orlando, Florida location.

The selected candidate must be able to obtain a secret clearance. A company-sponsored Interim Secret is required to start.

Basic Qualifications

• Bachelor of Science in Electrical Engineering or a related discipline, or equivalent education/experience.
• Proven experience leading FPGA design teams or managing FPGA development projects.
• Proficiency in hardware description languages (VHDL, Verilog, and/or System Verilog).
• Experience with embedded System-on-Chip integration and hardware validation.
• Exposure to video and signal-processing implementations.
• Demonstrated ability to plan and manage technical, cost, and schedule objectives.

Desired skills

• Experience managing configuration control, preferably using Git Lab.
• Hands-on experience with AMD/Xilinx tools and devices, including Versal and Ultra Scale+ families.
• Expertise in High-Level Synthesis and proficiency with Vivado/Vitis design environments.
• Background in program and project planning, including Cost Account Management (CAM) experience.
• Strong troubleshooting and debugging skills for board-level testing and FPGA validation.
• Comprehensive knowledge of the ASIC/FPGA lifecycle: architecture, design, simulation, verification, integration, and test.
• Familiarity with video processing standards (e.g., HDMI, SDI) and related signal-processing algorithms.
• Experience collaborating with cross-functional engineering and program management teams in an Agile or iterative development environment.

EEO

Lockheed Martin is an equal opportunity employer. Qualified candidates will be considered without regard to legally protected characteristics.
The application window will close in 90 days; applicants are encouraged to apply within 5 - 30 days of the requisition posting date in order to receive optimal consideration.

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