FPGA Design Engineer Sr

Basic Qualifications

• Bachelors degree from an accredited college in a related discipline, or equivalent experience/combined education.
• Relevant experience with FPGA design and simulation verification.
• Familiarity of Synopsys EDA tools.

E2523: ASIC & FPGA Design Eng Sr

You will be the FPGA Design & Verification Engineer for the Lockheed Martin Advanced Technologies team. Our team creates cutting edge FPGA based solutions that power next generation defense and aerospace systems, delivering high performance computing, signal processing and real time control.

• Translating system requirements into detailed FPGA designs, writing HDL code (System Verilog preferred, VHDL acceptable) and generating synthesis, placement, routing and timing constraints.
• Developing self checking verification test benches using System Verilog and UVM to validate functional behaviour of each module.
• Running simulations with Synopsys VCS, analysing results, and iterating designs to meet performance, power and timing goals.
• Managing source control and continuous integration pipelines in Git Lab, tracking progress via Git Lab Issues and maintaining version controlled design artefacts.
• Collaborating with the Programmable Logic Design Lead and hardware, software and systems engineers to integrate FPGA designs into the overall product system.
• Performing board level integration, debugging and troubleshooting of existing FPGA implementations, and delivering design updates as required.
• Conducting timing analysis, power budgeting and resource utilisation studies to optimise device selection and FPGA utilisation.
• Documenting design specifications, verification plans, test results and release packages in accordance with Lockheed Martin design assurance processes.
• Supporting design review meetings, providing status updates and risk assessments to project leadership.
• Mentoring junior team members on HDL coding, verification methodologies and Git Lab workflow best practices.

Do you want to be part of a company culture that empowers employees to think big, lead with a growth mindset, and make the impossible a reality? We provide the resources and give you the flexibility to enable inspiration and focus. If you have the passion and courage to dream big, work hard, and have fun doing what you love then we want to build a better tomorrow with you.

We offer flexible work schedules to comprehensive benefits investing in your future and security, Learn more about Lockheed Martin’s comprehensive benefits package here.

This position is in Orlando. Discover more about our Orlando, Florida location.

MUST BE A U.S. CITIZEN - This position is located at a facility that requires special access. The selected candidate must be able to obtain a secret clearance.

• LM Design Experience
• Missile Experience
• MSEE, MSCE would be a plus.
• Experience with System‑Verilog, Verilog, C/C++, Matlab/Simulink, System Verilog languages;
  Synopsis Synplify, Synopsis VCS, NCSim, Chip Scope tool sets desired.
• Experience with Xilinx/AMD and Micro Semi/Microchip part families internal FPGA fabric and IP.
• FPGA design experience with tools noted above.
• Previous experience related to aerospace design techniques would be a plus.
• Prior experience with Lockheed Marin MFC is a plus
• Experience Implementing NSA algorithms (i.e. AES, counter mode, etc)
• Experience with management of Configuration Control (Git Lab preferred)
• Experience with Vivado, and Vitis FPGA toolsets
• Experience with UVM
• Experience with Simulink and HDL Coder
• Comfortable using digital oscilloscopes, spectrum analyzers, power meters, signal generators and other test equipment
• Experience with troubleshooting and debugging with board‑level testing and FPGA validation
• Experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test)

By applying to this job, you are expressing interest in this position and could be considered for other career opportunities where similar skills and requirements have been identified as a match. Should this match be identified you…