FPGA Design Engineer

Overview

FPGA Design Engineer with Radio experience (Onsite Role) in Ottawa, Ontario, Canada. Digital Signal Processing (DSP) is a must‑have skill for the role. Ideal candidate is an FPGA designer with Radio experience working with 4G/5G Radios.

• Works on unusually complex problems and provides highly innovative solutions. Uses independent judgment to accomplish goals and objectives. Leads teams, gives technical guidance, and communicates with senior management on progress.
• Identifies or creates solutions likely to contribute to the development of new company concepts. Sets standards and achieves cost targets for product cost through proper design choices, component selection, and supplier selection.
• Acts as a consultant on critical projects that impact long‑term organizational goals and objectives. Contributes to evaluations, project plans, and budgets for new products or updates to existing products.
• Mentors junior engineers and participates in technical reviews. May interact with customers to gather input and ensure alignment with requirements.

• Design & Architecture: Develop FPGA IP architecture for 4G/5G Radio Units. Contribute to system‑level design aligned with 3
  
  GPP and O‑RAN Alliance specifications.
• Implementation: Implement complex RTL blocks (Verilog/System Verilog) and integrate into larger systems. Optimize FPGA resource utilization and ensure timing closure.
• Validation & Testing: Define and execute verification plans using UVM and advanced techniques. Perform simulation and system‑level FPGA validation.
• Collaboration: Work closely with Radio Unit development teams for seamless integration. Partner with software teams to ensure hardware‑software interoperability. Mentor junior engineers and participate in technical reviews.

• Essential Requirements:
  • Proven experience in FPGA design and RTL development.
  • Expertise in /LTE/eCPRI/CPRI/PTP protocols and signal processing (DSP focus for telecommunications and wireless fronthaul/baseband).
  • Familiarity with JESD
    204B/C, Ethernet, PCIe, AXI, and high‑speed SERDES.
  • Tools:
    Quartus, Vivado, MATLAB/Simulink, HDL Coder.
  • Knowledge of UVM and verification methodologies. Strong understanding of 4G/5G Radio architecture and O‑RAN ecosystem.
  • Experience with Git/Git Hub and version control workflows.
• Desirable
  
  Skills:
  
  7+ years of FPGA design experience in wireless or high‑speed systems; experience in high‑volume wireless products and IP development; contributions to standards bodies or technical forums (O‑RAN, 3
  
  GPP).