Design Verification Engineer

About Voltai
Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.

About the Team

Backed by Silicon Valley's top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), CTOs of Synopsys & Global Foundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.

About this Role
In this role, you will ensure silicon correctness through UVM-based environments, formal methods, and emulation. You'll collaborate with machine learning research engineers, verification engineers, and physical design teams to develop next-generation simulation engines for edge conditions and corner cases to guarantee robustness.

You might thrive if you have 5+ years of experience in

• System Verilog/UVM
• Functional coverage
• Assertions
• Regression infrastructure
• Debug tools