Senior Analog​/Mixed-Signal IC Design Engineer

Job Summary

We are seeking an experienced Analog/Mixed‑Signal IC Design Engineer to design and deliver high‑performance integrated circuits from concept through silicon validation and production. This role spans architecture, circuit design, and lab bring‑up, with significant ownership and direct impact on real products.

• Design and develop analog and mixed‑signal circuit blocks, including:
  • Data converters (ADC/DAC)
  • Amplifiers (LNA, TIA, op‑amps)
  • Bandgap references, biasing circuits, and regulators
• Define system architecture and drive trade‑offs across noise, linearity, power, area, and bandwidth.
• Perform transistor‑level design, simulation, and optimization using industry‑standard tools.
• Develop behavioral models (Verilog‑A / System Verilog RNM) for system‑level verification and architectural exploration.
• Work closely with layout to ensure performance through parasitic‑aware design and careful floor planning.
• Run post‑layout simulations and sign‑off analyses (PVT, Monte Carlo, corner analysis).
• Collaborate with digital and verification teams for robust mixed‑signal integration.
• Drive/manage silicon bring‑up, debug, and lab characterization.
• Drive clear design documentation and participate in design reviews.
• Take ownership of deliverables and drive work to completion, including under tight timelines.
• Contribute across disciplines as needed, including outside primary specialization.
• Maintain organized workflows to manage simulations, design iterations, and analysis results.

• MS or PhD in Electrical Engineering or related field.
• Strong fundamentals in analog circuit design and device physics.
• Proven experience designing and taping out analog or mixed‑signal ICs.
• Expertise in CMOS or SiGe design across one or more process nodes.
• Proficiency with SPICE‑based simulation tools (e.g., Spectre, HSPICE).
• Deep understanding of noise, mismatch, stability, and nonlinearity.
• Ability to design from first principles and solve complex circuit problems creatively.
• Strong organizational skills to manage large design spaces (corners, Monte Carlo, trade‑offs).
• Demonstrated ownership mindset with a focus on delivering high‑quality results.

• Experience with data converters, RF/analog front‑ends, or high‑speed interfaces.
• Experience with both mature and advanced process nodes (FinFET or beyond) a plus.
• Hands‑on experience with silicon validation and lab debugging.
• Experience contributing across full chip development cycles.
• Experience with Cadence Virtuoso design environment.
• Hands‑on experience with layout, tapeout, and bench validation.
• Familiarity with System Verilog RNM and/or Verilog‑A modeling.

• First‑principles thinking and strong engineering judgment.
• Ability to navigate complex trade‑offs across performance, power, and area.
• Ownership from architecture through silicon validation.
• Clear and effective communication in cross‑functional teams.
• Intellectual curiosity and a drive to continuously learn new tools, domains, and techniques.
• Flexibility to contribute beyond core responsibilities in a fast‑paced environment.
• Strong organizational discipline when working across many design iterations.
• Receptiveness to feedback and commitment to continuous improvement.
• Reliability and accountability in meeting commitments.
• Willingness to go the extra mile to meet critical milestones.

Psi Quantum provides equal employment opportunity for all applicants and employees. Psi Quantum does not unlawfully discriminate on the basis of race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, gender expression, national origin, ancestry, citizenship, age, physical or mental disability, military or veteran status, marital status, domestic partner status, sexual orientation, genetic information, or any other basis protected by applicable laws.