Layout Verification​/PEX Engineer

Psi Quantum is building quantum computers using silicon photonics technology. This role supports the physical and electrical verification of photonic integrated circuits, validating electrical routing and running design rule checks, layout versus schematic verification, and parasitic extraction flows prior to tapeout.

• Run established DRC, LVS, ERC, antenna, density, and parasitic extraction flows using existing scripts, runsets, and foundry PDK decks
• Validate electrical routing in photonic integrated circuit layouts, including bias lines, heaters, phase shifters, modulators, monitor structures, control signals, and electrical I/O interfaces
• Generate extracted netlists and extracted views for post-layout electrical simulation
• Maintain organized logs, reports, run directories, and status trackers
• Support block-level and chip-level verification activities and work with layout and design engineers to resolve verification issues prior to tapeout

• Bachelor's degree in Electrical Engineering, Physics, Microelectronics, or related field, or equivalent experience
• Basic knowledge of IC layout and physical verification concepts
• Exposure to DRC, LVS, or parasitic extraction
• Familiarity with Linux or Unix environments
• Strong attention to detail and ability to follow established procedures
• Demonstrated interest in quantum computing

• Exposure to analog/mixed-signal ICs or custom IC layout
• Experience with Cadence Virtuoso, Siemens Calibre, Cadence Pegasus/PVS, or Cadence Quantus EDA tools
• Familiarity with post-layout simulation flows and extracted netlists
• Basic scripting experience in Python
• Exposure to silicon photonics, photonic integrated circuits, or optoelectronics

U.S. Base Pay Range: $110,000–$150,000 USD (outside Bay Area); $150,000–$170,000 USD (Bay Area, within 50 miles of Palo Alto HQ). Full-time roles are eligible for equity and benefits.