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Layout Verification​/PEX Engineer

Job in Palo Alto, Santa Clara County, California, 94306, USA
Listing for: PsiQuantum
Full Time position
Listed on 2026-06-21
Job specializations:
  • Engineering
    Electrical Engineering, Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 125000 - 150000 USD Yearly USD 125000.00 150000.00 YEAR
Job Description & How to Apply Below
Position: Layout Verification / PEX Engineer

Psi Quantum’s mission is to build the first useful quantum computers—machines capable of delivering the breakthroughs the field has long promised. Since our founding in 2016, our singular focus has been to build and deploy million-qubit, fault‑tolerant quantum systems.

Quantum computers harness the laws of quantum mechanics to solve problems that even the most advanced supercomputers or AI systems will never reach. Their impact will span energy, pharmaceuticals, finance, agriculture, transportation, materials, and other foundational industries.

Our architecture and approach is based on silicon photonics. By leveraging the advanced semiconductor manufacturing industry—including partners like Global Foundries—we use the same high‑volume processes that already produce billions of chips for telecom and consumer electronics. Photonics offers natural advantages for scale: photons don’t feel heat, are immune to electromagnetic interference, and integrate with existing cryogenic cooling and standard fiber‑optic infrastructure.

In 2024, Psi Quantum announced government‑funded projects to support the build‑out of our first utility‑scale quantum computers in Brisbane, Australia, and Chicago, Illinois. These initiatives reflect a growing recognition that quantum computing will be strategically and economically defining—and that now is the time to scale.

Psi Quantum also develops the algorithms and software needed to make these systems commercially valuable. Our application, software, and industry teams work directly with leading Fortune 500 companies—including Lockheed Martin, Mercedes‑Benz, Boehringer Ingelheim, and Mitsubishi Chemical—to prepare quantum solutions for real‑world impact.

Quantum computing is not an extension of classical computing. It represents a fundamental shift—and a path to mastering challenges that cannot be solved any other way. The potential is enormous, and we have a clear path to make it real.

Come join us.

Job Summary

The Psi Quantum Foundry Engineering team develops and supports a silicon photonics technology platform in collaboration with our development partners. This work includes enabling new materials, process modules, and technology capabilities required to support Psi Quantum’s product development roadmap for a commercially useful quantum computer.

The Layout Verification / Parasitic Extraction Engineer will support the physical and electrical verification of photonic integrated circuits within Psi Quantum’s silicon photonics technology platform. This role will focus on validating the electrical routing associated with photonic circuits, including routing for photonic devices, bias lines, heaters, phase shifters, modulators, monitor structures, control signals, and electrical I/O interfaces.

This is a hands‑on execution role suited for a detail‑oriented engineer who is comfortable working with EDA tools. The engineer will run established DRC, LVS, ERC, antenna, density, and parasitic extraction flows; review verification reports; generate extracted outputs; and work with layout and design engineers to identify and resolve layout verification issues prior to tapeout.

Responsibilities
  • Run established DRC, LVS, ERC, antenna, density, and parasitic extraction flows using existing scripts, runsets, and foundry PDK decks.
  • Validate electrical routing in photonic integrated circuit layouts, including routing for photonic devices, bias lines, heaters, phase shifters, modulators, monitor structures, control signals, and electrical I/O interfaces.
  • Generate extracted netlists and extracted views for post‑layout electrical simulation.
  • Maintain organized logs, reports, run directories, and status trackers.
  • Support block‑level and chip‑level verification activities prior to tapeout.
Experience / Qualifications

Required qualifications:

  • Bachelor’s degree in Electrical Engineering, Physics, Microelectronics, or related field, or equivalent experience.
  • Basic knowledge of IC layout and physical verification concepts.
  • Exposure to DRC, LVS, or parasitic extraction.
  • Familiarity with Linux or Unix environments.
  • Strong attention to detail and ability to follow established procedures.
  • Good communication and…
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